Test for weak SRAM cells

ABSTRACT

A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step  100 ), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step  102 ). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step  104 ), the bit lines are then shorted together (step  106 ), the word lines are disabled (step  108 ) and the bit lines are released (step  110 ). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step  112 ). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as “weak” (step  114 ).

This invention relates generally to static random access memory (SRAM)and, more particularly, to a method and apparatus for detecting weakSRAM cells.

A static RAM is a memory chip that requires power to hold its content,i.e. it retains data bits in its memory as long as power is beingsupplied. It is made up of a flip-flop circuit that lets current flowthrough one side or the other based on which one of two selecttransistors is activated. Unlike Dynamic RAM (DRAM), static RAM does notrequire refresh circuitry for periodically refreshing the cells. SRAMalso provides faster access to data than DRAM. However, they also takeup more space, use more power and tend to be more expensive. SRAM iscommonly used for a computer's cache memory and as part of the randomaccess memory digital-to-analogue converter on a video card, forexample.

FIG. 1 of the drawings illustrates a commonly-used six-transistor (6T)SRAM cell. A first inverter 100 comprising a P-channel transistor 102and an N-channel transistor 104, and a second inverter 200 comprising aP-channel transistor 202 and an N-channel transistor 204 areinterconnected in a known fashion to form a latch. A first N-channelselect transistor 106 couples the latch to a first bit line BLB and asecond N-channel select transistor 108 couples the latch to a second bitline BL. The gates of the N-channel select transistors 106, 108 arecoupled to a word line WL.

The six-transistor (6T) CMOS SRAM cell described above offers manyadvantages over the conventional four-transistor (4T) SRAM cell formicroprocessor or microcontroller designs, including the potential forperfect data retention because of its active pull-up PMOS transistors.However, this perfect data retention potential has not previously beenrealized, because some open-circuit defects, often called weak defects,are known to cause retention failures. This type of defect, typicallycaused by factors such as resistive defects, excessive process shifts,transistor mismatch, IR drops, etc., can cause unpredictable dataretention failures that are process, temperature and time dependent. Assuch retention failure tends to be random because cells are not entirelydamaged and retention failure (characterized by state flipping) istriggered only under certain operating conditions, such as electricaldisturbance (e.g. power supply noise), read/write cell disturbance, etc.during normal operation of the SRAM. As a result, the conventionalretention detection technique of high-temperature bakes and testalgorithms such as N-March may not detect this type of fault.

For the purpose of the following, we can define weak cells as thosecells whose static noise margin (SNM) is close to zero and thus suchcells can inadvertently flip their state. SNM is a measure of the logiccircuit's tolerance to noise in either of the states, i.e. by how muchcan the input voltage change without disturbing the present logic state.In other words, the SNM represents a measure of cell robustness.Referring to FIG. 2 of the drawings, there is illustrated a transferfunction of a memory cell with highlighted static noise margins. The SNMis defined as the side of the maximum square that can be embeddedbetween the transfer characteristics of the two cell inverters. Points Xand Y on the characteristics represent two stable states and theintersection point Z represents the meta-stable point. A smalldisturbance around Z towards X or Y will cause the cell to flip to stateX or Y respectively.

The types of defects referred to above tend to involve one or moretransistors with undesired electrical-parameter shifts, e.g. shiftedthreshold voltage, decreased effective transistor length, etc., as wellas “weak-ohmic” electrical opens and shorts due to resistive defects.These defects will be referred to hereinafter as “weak defects”. U.S.Pat. No. 5,034,923 describes three weak defect detection procedures tofully test the inverters of an SRAM circuit for the presence of weakdefects.

The first weak defect detection procedure can be summarized as follows,with reference back to FIG. 1 of the drawings. First, bit line BLB isprecharged to a low logic state (i.e. its voltage is brought to a valuebelow the threshold voltages of the transistors). Then, the output ofthe inverter being tested (say 100) is coupled to bit lines BLB and BLby driving the word line WL to a high logic state (i.e. its voltage isdriven to a value above the threshold voltages of the transistors),rendering transistors 106, 108 conductive. Then bit line BL is driven toa low logic state. Finally, the logic state of bit line BLB is sensed.

The second weak detection procedure is similar to the first, but withthe logical sense of the states of BLB and BL reversed. In other words,BLB is precharged to a high logic state, then WL is driven to a highstate, then BL is driven to a high logic state and the state of BLB issensed.

As is apparent, the result of each of the first two procedures will bethat the logic state of BLB will change from its precharged state if theinverter 100 is properly functioning. In other words, BLB should be in ahigh state after the first procedure and in a low state after thesecond.

The third weak defect detection procedure described in U.S. Pat. No.5,034,923 is designed to detect several instances of soft defects notdetectable by the first two procedures. This procedure involves holdingthe state of BL high and sensing the amount of current leaking throughthe inverter 100. A current sensor coupled into the Vdd supply line forthe SRAM cell detects if the leakage current exceeds a pre-selectedlimit, in which case the cell is identified as defective.

Referring to FIG. 3 of the drawings, there is illustrated the transfercharacteristics of a good SRAM cell (solid line) and a weak SRAM cell(broken line). The axes represent the node voltages which in turn areproportional to the bitline voltages. VM_(good) and VM_(weak) representthe metastability points of a good and a weak cell. If an SRAM cellinternal node is brought to the level of VM, then a small voltageincrement will flip the cell towards the direction of this increment.Points X₁, Y₁ (X₂, Y₂) on the transfer characteristic represent thestable states Z₁ (Z₂)—the metastable states of the good (weak) cellrespectively. As is apparent from FIG. 3, the weak cell has asignificantly smaller SNM than that of the good cell.

However, not all cells have the same transfer characteristics, that isto say, the meta-stable points may vary between cells. The meta-stablepoints may also change due to technology and circuit design. Stillfurther, customer requirements may vary depending on the targetapplication. The test procedures described in U.S. Pat. No. 5,034,923are somewhat unwieldy in that the test voltages cannot be changed totake these issues into account. This significantly restricts theapplication field of the described method. Moreover, the techniquesdescribed in U.S. Pat. No. 5,034,923 involve activating each word linein an array individually, such that the time it takes to perform theweak cell detection procedures is proportional to the number of wordlines in an array, i.e. testing times are relatively long.

We have now devised an arrangement which overcomes the problems outlinedabove.

Thus, in accordance with a first aspect of the present invention, thereis provided apparatus for testing a static random access memory (SRAM)cell for the presence of a weak defect, the SRAM cell having an initiallogic state and comprising a flip-flop circuit connected between two bitlines and coupled to a word line, the apparatus comprising:

-   a) means for pre-charging at least one of said bit lines to a    predetermined level;-   b) means for enabling said word line; and-   c) means for determining, after said word line has been enabled, the    logic state of the SRAM cell to determine if the logic state has    changed from said initial logic state; characterized in that the    apparatus further comprises means for programming a trip voltage    based on specific cell criterion and/or characteristics, and means    for driving, after said word line has been enabled and before said    logic state is determined, at least one of said bit lines, or a node    voltage proportional thereto, to said trip voltage.

Also in accordance with the first aspect of the present invention, thereis provided a method for testing a static random access memory (SRAM)cell for the presence of a weak defect, the SRAM cell having an initiallogic state and comprising a flip-flop circuit connected between two bitlines and coupled to a word line, the method comprising the steps of:

-   a) pre-charging at least one of said bit lines to a predetermined    level;-   b) enabling said word line; and-   c) determining, after said word line has been enabled, the logic    state of the SRAM cell to determine if the logic state has changed    from said initial logic state; characterized in that the method    further comprises the steps of programming a trip voltage based on    specific cell criterion and/or characteristics, and driving, after    said word line has been enabled and before said logic state is    determined, at least one of said bit lines, or a node voltage    proportional thereto, to said trip voltage.

The detection threshold (or trip voltage) programmability of theapparatus and method according to the first aspect of the presentinvention allows the detection threshold to be varied in order tosatisfy different pass criteria. As a result, the method according tothe first aspect of the invention is significantly more versatile thanthat of the prior art.

In accordance with a second aspect of the present invention, there isprovided apparatus for testing a static random access memory (SRAM)array for the presence of weak defects, the memory array comprising aplurality of SRAM cells each having an initial logic state, a pair ofbit lines to which each SRAM cell is connected, each SRAM cell beingcoupled to a respective word line, the apparatus comprising means forpre-charging at least one of said bit lines to a predetermined level,means for enabling said word lines, means for driving at least one ofsaid bit lines, or a node voltage proportional thereto, to apredetermined trip voltage, means for identifying the logic state ofeach of the SRAM cells after said at least one bit line, or node voltageproportional thereto, has been driven to said predetermined trip voltageto determine if the logic state of any of the cells has changed fromsaid initial logic state, and means for marking or otherwise identifyingas weak those cells whose logic state has been determined to havechanged from said initial logic state; characterized in that said meansfor enabling said word lines comprises means for enabling substantiallysimultaneously all of said word lines in said memory array.

Also in accordance with the second aspect of the present invention,there is provided a method for testing a static random access memory(SRAM) array for the presence of weak defects, the memory arraycomprising a plurality of SRAM cells each having an initial logic state,a pair of bit lines to which each SRAM cell is connected, each SRAM cellbeing coupled to a respective word line, the method comprising the stepsof pre-charging at least one of said bit lines to a predetermined level,enabling said word lines, driving at least one of said bit lines, or anode voltage proportional thereto, to a predetermined trip voltage,identifying the logic state of each of the SRAM cells after said atleast one bit line, or node voltage proportional thereto, has beendriven to said predetermined trip voltage to determine if the logicstate of any of the cells has changed from said initial logic state, andmarking or otherwise identifying as weak those cells whose logic statehas been determined to have changed from said initial logic state;characterized in that said step of enabling said word lines comprisesenabling substantially simultaneously all of said word lines in saidmemory array.

Because the apparatus and method of the second aspect of the inventioninvolves parallel word line activation, all of the cells in an array canbe tested in much less time than in the single word line activationtechniques of the prior art.

In a preferred embodiment, the trip voltage is programmed according tothe ratio of 0's and 1's contained in the SRAM cells. For the purposesof this specification, a weak cell can be considered to be defined ashaving a significantly lower static noise margin than that of a goodSRAM cell.

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiments described hereinafter.

Embodiments of the present invention will now be described by way ofexamples only and with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram illustrating the configuration of aconventional six-transistor SRAM cell;

FIG. 2 illustrates a transfer function of a memory cell with highlightedstatic noise margins;

FIG. 3 illustrates the transfer functions of a good and weak SRAM cellrespectively;

FIG. 4 illustrates V_(TEST) as a function of R for BL and BLB;

FIG. 5 is a schematic flow diagram illustrating a method according to anexemplary embodiment of the present invention;

FIG. 6 is a circuit diagram illustrating apparatus according to a firstexemplary embodiment of the present invention;

FIG. 7 is a graph illustrating simulation results of operation of theapparatus of FIG. 6;

FIG. 8 is a circuit diagram illustrating apparatus according to a secondexemplary embodiment of the present invention;

FIG. 9 is a graph illustrating the behavior of bit line voltages duringoperation of the apparatus of FIG. 8; and

FIG. 10 is a graph illustrating the correct behavior of the apparatus ofFIG. 8 when signal WD is timely issued.

Referring to FIGS. 1 and 3 of the drawings, let us assume that node 1 ofan SRAM cell has logic state “1” and that the bit lines are charged to aknown value (say Vdd/2). Now assume that by certain manipulation on thebit line bar voltage, V_(node 1) is brought down from a stable state ‘X’to V_(TEST) by means of the method according to an exemplary embodimentof the present invention, while the bit line is left floating. V_(TEST)represents the programmable weak cell detection threshold. As isapparent from FIG. 3 of the drawings, the weak cell will fail if(Vdd−V_(TEST))<Vdd−VM_(weak)), whereas the good cell will retain itsstate.

Voltage level V_(TEST) crosses the good cell transfer characteristics atpoints “1” and “2” and it crosses the weak cell transfer characteristicsat points “3” and “4”, as shown in FIG. 3. Node 1 of the good cell willretain its value (state “1”) while node 1 of the weak cell will flip tostate “0”. The arrows in FIG. 3 show the direction of the transfercharacteristic dynamics in this case.

The above-described principle is utilized in the method according to thefollowing exemplary embodiments of the present invention, i.e. all thecells which flip at the node voltage above V_(TEST) are deemed weak andare sorted out.

$\;{{{Let}\mspace{14mu}{us}\mspace{14mu}{now}\mspace{14mu}{define}\mspace{14mu}{the}\mspace{14mu}{ratio}\mspace{14mu} R} = \frac{\begin{matrix}{{number}\mspace{14mu}{of}\mspace{14mu}{cells}\mspace{14mu}{with}\mspace{14mu}{state}} \\{\mspace{11mu}{{``1"}\mspace{14mu}{in}\mspace{14mu} a\mspace{14mu}{given}\mspace{14mu}{column}}}\end{matrix}}{\mspace{14mu}\begin{matrix}{{total}\mspace{14mu}{number}\mspace{14mu}{of}\mspace{14mu}{cells}} \\{{in}\mspace{14mu}{the}\mspace{14mu}{same}\mspace{14mu}{column}}\end{matrix}}}$

In this definition, it is assumed that the cells not having state “1”are written state “0”, as can be seen from the definition of R, Rε[0,1].

Assume that a predetermined 0/1 pattern R is written to a memory arrayof SRAM cells. Now, if all of the word lines are enabled at the sametime, a programmable V_(TEST) voltage on the bit lines can be achieved.Different V_(TEST) voltages and therefore the weak cell detectionthreshold values can be obtained by changing the ratio R. The dependenceof V_(TEST) on R for BL and BLB is illustrated in FIG. 4 of thedrawings.

Referring to FIG. 5 of the drawings, an embodiment of a method accordingto the present invention will be described by way of example only. Atstep 100, a 0/1 ratio is written to the memory array. At step 102, thebit lines BL and BLB are precharged and equalized to V_(TEST). V_(TEST)is selected or programmed according to the 0/1 ratio of cells, asdescribed above with reference to FIG. 4 of the drawings. At step 104,the word lines associated with all of the SRAM cells in the array areenabled in parallel, and at step 106 the bit lines BL and BLB areshorted together. The word lines are then disabled (at step 108) and thebit lines are released (at step 110). The contents of the SRAM array arethen read and compared against the current 0/1 ratio as written to thearray at step 100 (step 112). Any cells whose contents do not match theoriginal 0/1 ratio (i.e. whose state has flipped) are marked orotherwise identified as “weak” (at step 114). The 0/1 ratio is inverted(at step 116) and steps 100 to 114 are repeated for the inverted 0/1ratio. This inverted 0/1 ratio is used to detect weak cells that mayflip in the opposite direction. This method is repeated for all 0/1ratios required to be tested.

Referring to FIG. 6 of the drawings, apparatus according to a firstexemplary embodiment of the present invention will now be described. Theillustrated apparatus comprises one column of memory cells 600, with twocross-coupled PMOS transistors 601, 602 to pull up the bit lines, threeother PMOS transistors 603, 604, 605 to precharge the bit lines to Vdd,one NMOS transistor 606 to short the bit lines together, appropriatelogic 607 to issue the weak-detect (WD) signal, an a word line decoder608 for simultaneous enablement of the word lines.

The weak cell detection phase starts by programming the trip pointV_(TEST) that is necessary to detect cells with a low SNM. This is doneby writing a predetermined number of cells with either a ‘1’ or a ‘0’state. The bit lines are then precharged to Vdd by the transistors 603,604, 605. After this bit line precharging finishes, all word lines aresimultaneously enabled, thereby connecting in parallel all cells 600 ofthe same column. Under this configuration, access transistors share acommon gate and a common bit line node. The other access transistorterminal is connected either to the ground or Vdd through thecorresponding NMOS or PMOS driver transistors of the memory cell. Theaccess transistors operate as resistors, dividing the power supplyvoltage on either bit line between Vdd and ground depending on theequivalent DC path resistance. For example, a bit line node is held atVdd/2 when 50% of the cells are in state ‘0’, because the pathresistance to ground and Vdd is the same, i.e. R=0.5.

The graph of FIG. 7 illustrates simulation results of theabove-described implementation. The curves correspond to the bit linesBL (702), BLB (704), the weak detection signal WD (706) and the cell'sstate voltages (708). The upper graph 700 a illustrates the situationwhereby the bit lines are timely shorted together, whereas the lowergraph 700 b illustrates the situation whereby the bit lines are shortedtogether too late. In the latter case, it can be seen how the internalstate of the cell flips to state ‘0’. Note that when the word lines areenabled, the bit line capacitance discharges according to the timeconstant created by the equivalent path resistance. Further, if thedischarge voltage drops below Vdd/2 (which could also be the metastablepoint), even the good cells will flip, which may cause one of the bitlines to be pulled to ground and restore the other bit line to Vdd.Thus, to prevent the cells from reaching the metastable point, the bitlines are shorted together through an NMOS pass transistor 606 usingsignal WD. This causes the voltages at the bit lines to remain constantat around Vdd/2 while the cell dynamic finds a new equilibrium. In otherwords, the bit lines are not pulled to complementary logical values.However, a bit line voltage around Vdd/2 is sufficient to flip weakcells. For a ratio R≠0.5, the corresponding path resistances to Vdd andground are also different and thus the bit line voltage is simply pulledearlier above or below Vdd/2.

Referring to FIG. 8 of the drawings, apparatus according to a secondexemplary embodiment of the invention comprises a column of memory cells800, pull-up and pull-down MOS transistors 803, 804 tied to the bitlines, a CMOS switch 807 comprising transistors 805, 806 to short thebit lines together, and appropriate logic 808 to enable all word linessimultaneously and to test-precharge the bit lines.

In contrast with the apparatus described with reference to FIG. 6, inthis embodiment of the apparatus, the bit lines are precharged to Vddand to ground, rather than only to Vdd. When the word lines are enabled,the bit line precharging works in a similar way to that described withreference to FIG. 6 to write operation forcing all the cells to have thesame state. Although the precharging and word line enabling stages havebeen described herein as being mutually exclusive, in practice, a smalloverlap exists between them. If this overlap is sufficiently long, eventhe good cells will flip. FIG. 9 illustrates this behavior in theabsence of the WD pulse. The upper graph 900 a depicts the case when agood cell flips due to an overlap between precharge and WL signals ofabout 120 ps. The lower graph 900 b shows the expected behavior when theoverlap is 60 ps. Fortunately, the time window of the overlap can becompensated by timely shorting together the bit lines, as illustrated inthe graph of FIG. 10.

Embodiments of the present invention have been described herein by wayof examples only, and it will be apparent to persons skilled in the artthat modifications and variations can be made to the describedembodiments without departing from the scope of the invention as definedin the appended claims. Further, the term ‘comprising’ does not precludeother elements or steps, ‘a’ or ‘an’ does not exclude a plurality, and asingle element or unit may fulfil the functions of several means recitedin the claims.

1. Apparatus for testing a static random access memory (SRAM) cell forthe presence of a weak defect, the SRAM cell having an initial logicstate and comprising a flip-flop circuit connected between two bit lines(BL, BLB) and coupled to a word line (WL), the apparatus comprising: a)means for pre-charging at least one of said bit lines (BL, BLB) to apredetermined level; b) means for enabling said word line (WL); and c)means for determining, after said word line (WL) has been enabled, thelogic state of the SRAM cell to determine if the logic state has changedfrom said initial logic state; characterized in that the apparatusfurther comprises means for programming a trip voltage based on specificcell criterion and/or characteristics, and means for driving, after saidword line (WL) has been enabled and before said logic state isdetermined, at least one of said bit lines (BL, BLB), or a node voltageproportional thereto, to said trip voltage.
 2. Apparatus according toclaim 1, wherein said trip voltage is programmed according to theinitial logic state of said SRAM cell.
 3. Apparatus according to claim2, comprising means for determining the initial logic state of each ofthe SRAM cells in the array, and programming said trip voltage accordingto the ratio of 0's and 1's contained therein.
 4. Apparatus according toclaim 3, comprising means for determining the logic state of all of saidSRAM cells after said word lines (WL) have been enabled and marking orotherwise identifying as weak those cells whose logic state isdetermined to have changed from said initial logic state.
 5. Apparatusaccording to claim 4, wherein a weak cell is defined as having asignificantly lower static noise margin than that of a good cell. 6.Apparatus according to claim 1 for testing an SRAM array for thepresence of weak cells, said SRAM array comprising a plurality of SRAMcells all connected between the same two bit lines (BL, BLB) and eachbeing coupled to a respective word line (WL).
 7. Apparatus according toclaim 6, wherein said means for enabling the word line (WL) comprisesmeans for enabling substantially simultaneously all of the word lines towhich said plurality of SRAM cells are respectively coupled. 8.Apparatus according to claim 1, comprising means for shorting togethersaid bit lines (BL, BLB) after said word line(s) has (have) beenenabled.
 9. Apparatus according to claim 8, wherein said means forshorting together the bit lines comprises a MOS transistor connectedbetween said bit lines.
 10. Apparatus according to claim 9, wherein saidmeans for shorting together the bit lines comprises an NMOS transistor.11. Apparatus according to claim 8, wherein said means for shortingtogether the bit lines (BL, BLB) comprises a CMOS switch connectedbetween the bit lines.
 12. Apparatus according to claim 11, wherein saidCMOS switch comprises two transistors.
 13. Apparatus for testing astatic random access memory (SRAM) array for the presence of weak cells,the memory array comprising a plurality of SRAM cells each having aninitial logic state, a pair of bit lines (BL, BLB) to which each SRAMcell is connected, each SRAM cell being coupled to a respective wordline (WL), the apparatus comprising means for pre-charging at least oneof said bit lines (BL, BLB) to a predetermined level, means for enablingsaid word lines (WL), means for driving at least one of said bit lines,or a node voltage proportional thereto, to a predetermined trip voltage,means for identifying the logic state of each of the SRAM cells aftersaid at least one bit line, or node voltage proportional thereto, hasbeen driven to said predetermined trip voltage to determine if the logicstate of any of the cells has changed from said initial logic state, andmeans for marking or otherwise identifying as weak those cells whoselogic state has been determined to have changed from said initial logicstate; characterized in that said means for enabling said word linescomprises means for enabling substantially simultaneously all of saidword lines in said memory array.
 14. Apparatus according to claim 13,comprising means for programming said predetermined trip voltage basedon specific cell criterion and/or characteristics.
 15. Apparatusaccording to claim 14, wherein said means for programming said tripvoltage does so based on the ratio of opposing initial logic states ofsaid SRAM cells.
 16. A method for testing a static random access memory(SRAM) cell for the presence of a weak defect, the SRAM cell having aninitial logic state and comprising a flip-flop circuit connected betweentwo bit lines (BL, BLB) and coupled to a word line (WL), the methodcomprising the steps of: a) pre-charging at least one of said bit linesto a predetermined level; b) enabling said word line; and c)determining, after said word line has been enabled, the logic state ofthe SRAM cell to determine if the logic state has changed from saidinitial logic state; characterized in that the method further comprisesthe steps of programming a trip voltage based on specific cell criterionand/or characteristics, and driving, after said word line has beenenabled and before said logic state is determined, at least one of saidbit lines, or a node voltage proportional thereto, to said trip voltage.17. A method for testing a static random access memory (SRAM) array forthe presence of weak cells, the memory array comprising a plurality ofSRAM cells each having an initial logic state, a pair of bit lines (BL,BLB) to which each SRAM cell is connected, each SRAM cell being coupledto a respective word line (WL), the method comprising the steps ofpre-charging at least one of said bit lines to a predetermined level,enabling said word lines, driving at least one of said bit lines, or anode voltage proportional thereto, to a predetermined trip voltage,identifying the logic state of each of the SRAM cells after said atleast one bit line, or node voltage proportional thereto, has beendriven to said predetermined trip voltage to determine if the logicstate of any of the cells has changed from said initial logic state, andmarking or otherwise identifying as weak those cells whose logic statehas been determined to have changed from said initial logic state;characterized in that said step of enabling said word lines comprisesenabling substantially all of said word lines in said memory array.